Francky Catthoor

This book provides a holistic view of workload-dependent mitigation techniques for performance variability. The authors describe the use of design-time profiling information to reduce the uncertainties in future execution time calculation at run time, thereby offering the best option for minimizing system costs while reducing missed deadlines. Readers are introduced to an approach that combines dynamic voltage and frequency scaling (DVFS) with heterogeneous datapaths (HDP), enabling users to tackle performance variability of multiple timescales down to the sub-millisecond level.

Modern computing engines—CPUs, GPUs, and NPUs—require extensive SRAM for cache designs, driven by the increasing demand for higher density, performance, and energy efficiency. This book delves into two primary areas within ultra-scaled technology nodes: (1) advancing SRAM bitcell scaling and (2) exploring innovative subarray designs to enhance power-performance-area (PPA) metrics across technology nodes. The first part of the book utilizes a bottom-up design-technology co-optimization (DTCO) approach, employing a dedicated PPA simulation framework to evaluate and identify the most promising strategies for SRAM bitcell scaling. It offers a comprehensive examination of SRAM bitcell scaling beyond 1 nm node, outlining a structured research cycle that includes identifying scaling bottlenecks, developing cutting-edge architectures with complementary field-effect transistor (CFET) technology, and addressing challenges such as process integration and routing complexities. Additionally, this book introduces a novel write margin methodology to better address the risks of write failures in resistance-dominated nodes. This methodology accounts for time-dependent parasitic bitline effects and incorporates timing setup of write-assist techniques to prevent underestimating the yield loss. In the second part, the focus shifts to a top-down DTCO approach due to the diminishing returns of bitcell scaling beyond 5 Å node at the macro level. As technology scales, increasing resistance and capacitance (RC) lead designers to adopt smaller subarray sizes to reduce effective RC and enhance subarray-level PPA. However, this approach can result in increased inter-subarray interconnect overhead, potentially offsetting macro-level improvements. This book examines the effects of various subarray sizes on macro-level PPA and finds that larger subarrays can significantly reduce interconnect overhead and improve the energy-delay-area product (EDAP) of SRAM macro. The introduction of the active interconnect (AIC) concept enables the use of larger subarray sizes, while integrating carbon nanotube FET as back-end-of-line compatible devices results in macro-level EDAP improvements of up to 65% when transitioning from standard subarrays to AIC divided subarrays. These findings highlight the future trajectory of SRAM subarray design in deeply scaled nodes.

This book provides novel theoretical foundations and experimental demonstrations of Spiking Neural Networks (SNNs) in tasks such as radar gesture recognition for IoT devices and autonomous drone navigation using a fusion of retina-inspired event-based camera and radar sensing. The authors describe important new findings about the Spike-Timing-Dependent Plasticity (STDP) learning rule, which is widely believed to be one of the key learning mechanisms taking place in the brain. Readers will be enabled to create novel classes of edge AI and robotics applications, using highly energy- and area-efficient SNNs

This book provides a holistic view of workload-dependent mitigation techniques for performance variability. The authors describe the use of design-time profiling information to reduce the uncertainties in future execution time calculation at run time, thereby offering the best option for minimizing system costs while reducing missed deadlines. Readers are introduced to an approach that combines dynamic voltage and frequency scaling (DVFS) with heterogeneous datapaths (HDP), enabling users to tackle performance variability of multiple timescales down to the sub-millisecond level.

Modern computing engines—CPUs, GPUs, and NPUs—require extensive SRAM for cache designs, driven by the increasing demand for higher density, performance, and energy efficiency. This book delves into two primary areas within ultra-scaled technology nodes: (1) advancing SRAM bitcell scaling and (2) exploring innovative subarray designs to enhance power-performance-area (PPA) metrics across technology nodes. The first part of the book utilizes a bottom-up design-technology co-optimization (DTCO) approach, employing a dedicated PPA simulation framework to evaluate and identify the most promising strategies for SRAM bitcell scaling. It offers a comprehensive examination of SRAM bitcell scaling beyond 1 nm node, outlining a structured research cycle that includes identifying scaling bottlenecks, developing cutting-edge architectures with complementary field-effect transistor (CFET) technology, and addressing challenges such as process integration and routing complexities. Additionally, this book introduces a novel write margin methodology to better address the risks of write failures in resistance-dominated nodes. This methodology accounts for time-dependent parasitic bitline effects and incorporates timing setup of write-assist techniques to prevent underestimating the yield loss. In the second part, the focus shifts to a top-down DTCO approach due to the diminishing returns of bitcell scaling beyond 5 Å node at the macro level. As technology scales, increasing resistance and capacitance (RC) lead designers to adopt smaller subarray sizes to reduce effective RC and enhance subarray-level PPA. However, this approach can result in increased inter-subarray interconnect overhead, potentially offsetting macro-level improvements. This book examines the effects of various subarray sizes on macro-level PPA and finds that larger subarrays can significantly reduce interconnect overhead and improve the energy-delay-area product (EDAP) of SRAM macro. The introduction of the active interconnect (AIC) concept enables the use of larger subarray sizes, while integrating carbon nanotube FET as back-end-of-line compatible devices results in macro-level EDAP improvements of up to 65% when transitioning from standard subarrays to AIC divided subarrays. These findings highlight the future trajectory of SRAM subarray design in deeply scaled nodes.

This book provides novel theoretical foundations and experimental demonstrations of Spiking Neural Networks (SNNs) in tasks such as radar gesture recognition for IoT devices and autonomous drone navigation using a fusion of retina-inspired event-based camera and radar sensing. The authors describe important new findings about the Spike-Timing-Dependent Plasticity (STDP) learning rule, which is widely believed to be one of the key learning mechanisms taking place in the brain. Readers will be enabled to create novel classes of edge AI and robotics applications, using highly energy- and area-efficient SNNs

This book defines and explores the problem of placing the instances of dynamic data types on the components of the heterogeneous memory organization of an embedded system, with the final goal of reducing energy consumption and improving performance. It is one of the first to cover the problem of placement for dynamic data objects on embedded systems with heterogeneous memory architectures, presenting a complete methodology that can be easily adapted to real cases and work flows. The authors discuss how to improve system performance and energy consumption simultaneously. Discusses the problem of placement for dynamic data objects on embedded systems with heterogeneous memory architectures;Presents a complete methodology that can be adapted easily to real cases and work flows;Offers hints on how to improve system performance and energy consumption simultaneously.

This book introduces a generic and systematic design-time/run-time methodology for handling the dynamic nature of modern embedded systems, without adding large safety margins in the design. The techniques introduced can be utilized on top of most existing static mapping methodologies to deal effectively with dynamism and to increase drastically their efficiency. This methodology is based on the concept of system scenarios, which group system behaviors that are similar from a multi-dimensional cost perspective, such as resource requirements, delay, and energy consumption. Readers will be enabled to design systems capable to adapt to current inputs, improving system quality and/or reducing cost, possibly learning on-the-fly during execution. Provides an effective solution to deal with dynamic system designIncludes a broad survey of the state-of-the-art approaches in this domainEnables readers to design for substantial cost improvements (e.g. energy reductions), by exploiting system scenariosDemonstrates how the methodology has been applied effectively on various, real design problems in the embedded system context

This book defines and explores the problem of placing the instances of dynamic data types on the components of the heterogeneous memory organization of an embedded system, with the final goal of reducing energy consumption and improving performance. It is one of the first to cover the problem of placement for dynamic data objects on embedded systems with heterogeneous memory architectures, presenting a complete methodology that can be easily adapted to real cases and work flows. The authors discuss how to improve system performance and energy consumption simultaneously. Discusses the problem of placement for dynamic data objects on embedded systems with heterogeneous memory architectures;Presents a complete methodology that can be adapted easily to real cases and work flows;Offers hints on how to improve system performance and energy consumption simultaneously.

This book introduces a generic and systematic design-time/run-time methodology for handling the dynamic nature of modern embedded systems, without adding large safety margins in the design. The techniques introduced can be utilized on top of most existing static mapping methodologies to deal effectively with dynamism and to increase drastically their efficiency. This methodology is based on the concept of system scenarios, which group system behaviors that are similar from a multi-dimensional cost perspective, such as resource requirements, delay, and energy consumption. Readers will be enabled to design systems capable to adapt to current inputs, improving system quality and/or reducing cost, possibly learning on-the-fly during execution. Provides an effective solution to deal with dynamic system designIncludes a broad survey of the state-of-the-art approaches in this domainEnables readers to design for substantial cost improvements (e.g. energy reductions), by exploiting system scenariosDemonstrates how the methodology has been applied effectively on various, real design problems in the embedded system context

This book discusses analysis, design and optimization techniques for streaming multiprocessor systems, while satisfying a given area, performance, and energy budget. The authors describe design flows for both application-specific and general purpose streaming systems. Coverage also includes the use of machine learning for thermal optimization at run-time, when an application is being executed. The design flow described in this book extends to thermal and energy optimization with multiple applications running sequentially and concurrently.

This book discusses analysis, design and optimization techniques for streaming multiprocessor systems, while satisfying a given area, performance, and energy budget. The authors describe design flows for both application-specific and general purpose streaming systems. Coverage also includes the use of machine learning for thermal optimization at run-time, when an application is being executed. The design flow described in this book extends to thermal and energy optimization with multiple applications running sequentially and concurrently.

This book provides a systematic and unified methodology, including basic principles and reusable processes, for dynamic memory management (DMM) in embedded systems. The authors describe in detail how to design and optimize the use of dynamic memory in modern, multimedia and network applications, targeting the latest generation of portable embedded systems, such as smartphones. Coverage includes a variety of design and optimization topics in electronic design automation of DMM, from high-level software optimization to microarchitecture-level hardware support. The authors describe the design of multi-layer dynamic data structures for the final memory hierarchy layers of the target portable embedded systems and how to create a low-fragmentation, cost-efficient, dynamic memory management subsystem out of configurable components for the particular memory allocation and de-allocation patterns for each type of application. The design methodology described in this book is based on propagating constraints among design decisions from multiple abstraction levels (both hardware and software) and customizing DMM according to application-specific data access and storage behaviors.

This book describes scalable and near-optimal, processor-level design space exploration (DSE) methodologies. The authors present design methodologies for data storage and processing in real-time, cost-sensitive data-dominated embedded systems. Readers will be enabled to reduce time-to-market, while satisfying system requirements for performance, area, and energy consumption, thereby minimizing the overall cost of the final design.

This book describes a new design approach for energy-efficient, Domain-Specific Instruction set Processor (DSIP) architectures for the wireless baseband domain. The innovative techniques presented enable co-design of algorithms, architectures and technology, for efficient implementation of the most advanced technologies. To demonstrate the feasibility of the author’s design approach, case studies are included for crucial functionality of advanced wireless systems with increased computational performance, flexibility and reusability. Designers using this approach will benefit from reduced development/product costs and greater scalability to future process technology nodes.

This book provides a systematic and unified methodology, including basic principles and reusable processes, for dynamic memory management (DMM) in embedded systems. The authors describe in detail how to design and optimize the use of dynamic memory in modern, multimedia and network applications, targeting the latest generation of portable embedded systems, such as smartphones. Coverage includes a variety of design and optimization topics in electronic design automation of DMM, from high-level software optimization to microarchitecture-level hardware support. The authors describe the design of multi-layer dynamic data structures for the final memory hierarchy layers of the target portable embedded systems and how to create a low-fragmentation, cost-efficient, dynamic memory management subsystem out of configurable components for the particular memory allocation and de-allocation patterns for each type of application. The design methodology described in this book is based on propagating constraints among design decisions from multiple abstraction levels (both hardware and software) and customizing DMM according to application-specific data access and storage behaviors.

This book features various, ultra low energy, variability resilient SRAM circuit design techniques for wireless sensor network applications. Conventional SRAM design targets area efficiency and high performance at the increased cost of energy consumption, making it unsuitable for computation-intensive sensor node applications. This book, therefore, guides the reader through different techniques at the circuit level for reducing energy consumption and increasing the variability resilience. It includes a detailed review of the most efficient circuit design techniques and trade-offs, introduces new memory architecture techniques, sense amplifier circuits and voltage optimization methods for reducing the impact of variability for the advanced technology nodes.

This book describes scalable and near-optimal, processor-level design space exploration (DSE) methodologies. The authors present design methodologies for data storage and processing in real-time, cost-sensitive data-dominated embedded systems. Readers will be enabled to reduce time-to-market, while satisfying system requirements for performance, area, and energy consumption, thereby minimizing the overall cost of the final design.

This book describes a new design approach for energy-efficient, Domain-Specific Instruction set Processor (DSIP) architectures for the wireless baseband domain. The innovative techniques presented enable co-design of algorithms, architectures and technology, for efficient implementation of the most advanced technologies. To demonstrate the feasibility of the author’s design approach, case studies are included for crucial functionality of advanced wireless systems with increased computational performance, flexibility and reusability. Designers using this approach will benefit from reduced development/product costs and greater scalability to future process technology nodes.

Modern consumers carry many electronic devices, like a mobile phone, digital camera, GPS, PDA and an MP3 player. The functionality of each of these devices has gone through an important evolution over recent years, with a steep increase in both the number of features as in the quality of the services that they provide. However, providing the required compute power to support (an uncompromised combination of) all this functionality is highly non-trivial. Designing processors that meet the demanding requirements of future mobile devices requires the optimization of the embedded system in general and of the embedded processors in particular, as they should strike the correct balance between flexibility, energy efficiency and performance. In general, a designer will try to minimize the energy consumption (as far as needed) for a given performance, with a sufficient flexibility. However, achieving this goal is already complex when looking at the processor in isolation, but, in reality, the processor is a single component in a more complex system. In order to design such complex system successfully, critical decisions during the design of each individual component should take into account effect on the other parts, with a clear goal to move to a global Pareto optimum in the complete multi-dimensional exploration space. In the complex, global design of battery-operated embedded systems, the focus of Ultra-Low Energy Domain-Specific Instruction-Set Processors is on the energy-aware architecture exploration of domain-specific instruction-set processors and the co-optimization of the datapath architecture, foreground memory, and instruction memory organisation with a link to the required mapping techniques or compiler steps at the early stages of the design. By performing an extensive energy breakdown experiment for a complete embedded platform, both energy and performance bottlenecks have been identified, together with the important relations between thedifferent components. Based on this knowledge, architecture extensions are proposed for all the bottlenecks.