Leibo Liu

This book is the second volume of a two-volume book set which introduces software-defined chips. In this book, the programming model of the software-defined chips is analyzed by tracing the coevolution of modern general-purpose processors and programming models. The enhancement in hardware security and reliability of the software-defined chips are described from the perspective of dynamic and partial reconfiguration. The challenges and prospective trends of software-defined chips are also discussed. Current applications in the fields of artificial intelligence, cryptography, 5G communications, etc., are presented in detail. Potential applications in the future, including post-quantum cryptography, evolutionary computing, etc., are also discussed. This book is suitable for scientists and researchers in the areas of electrical and electronic engineering and computer science. Postgraduate students, practitioners and professionals in related areas are also potentially interested inthe topic of this book.

This is the first book of a two-volume book set which introduces software defined chips. In this book, it introduces the conceptual evolution of software defined chips from the development of integrated circuits and computing architectures. Technical principles, characteristics and key issues of software defined chips are systematically analyzed. The hardware architecture design methods are described involving architecture design primitives, hardware design spaces and agile design methods. From the perspective of the compilation system, the complete process from high-level language to configuration contexts is introduced in detail. This book is suitable for scientists and researchers in the areas of electrical and electronic engineering and computer science. Postgraduate students, practitioners and professionals in related areas are also potentially interested in the topic of this book.

This book is the second volume of a two-volume book set which introduces software-defined chips. In this book, the programming model of the software-defined chips is analyzed by tracing the coevolution of modern general-purpose processors and programming models. The enhancement in hardware security and reliability of the software-defined chips are described from the perspective of dynamic and partial reconfiguration. The challenges and prospective trends of software-defined chips are also discussed. Current applications in the fields of artificial intelligence, cryptography, 5G communications, etc., are presented in detail. Potential applications in the future, including post-quantum cryptography, evolutionary computing, etc., are also discussed. This book is suitable for scientists and researchers in the areas of electrical and electronic engineering and computer science. Postgraduate students, practitioners and professionals in related areas are also potentially interested inthe topic of this book.

This is the first book of a two-volume book set which introduces software defined chips. In this book, it introduces the conceptual evolution of software defined chips from the development of integrated circuits and computing architectures. Technical principles, characteristics and key issues of software defined chips are systematically analyzed. The hardware architecture design methods are described involving architecture design primitives, hardware design spaces and agile design methods. From the perspective of the compilation system, the complete process from high-level language to configuration contexts is introduced in detail. This book is suitable for scientists and researchers in the areas of electrical and electronic engineering and computer science. Postgraduate students, practitioners and professionals in related areas are also potentially interested in the topic of this book.

This book focuses on the design methods for reconfigurable computing processors for cryptographic algorithms. It covers the dynamic reconfiguration analysis of cryptographic algorithms, hardware architecture design, and compilation techniques for reconfigurable cryptographic processors, and also presents a case study of implementing the reconfigurable cryptographic processor “Anole” designed by the authors’ team. Moreover, it features discussions on countermeasures against physical attacks utilizing partially and dynamically reconfigurable array architecture to enhance security, as well as the latest trends for reconfigurable cryptographic processors. This book is intended for research scientists, graduate students, and engineers in electronic science and technology, cryptography, network and information security, as well as computer science and technology.

This book focuses on the design methods for reconfigurable computing processors for cryptographic algorithms. It covers the dynamic reconfiguration analysis of cryptographic algorithms, hardware architecture design, and compilation techniques for reconfigurable cryptographic processors, and also presents a case study of implementing the reconfigurable cryptographic processor “Anole” designed by the authors’ team. Moreover, it features discussions on countermeasures against physical attacks utilizing partially and dynamically reconfigurable array architecture to enhance security, as well as the latest trends for reconfigurable cryptographic processors. This book is intended for research scientists, graduate students, and engineers in electronic science and technology, cryptography, network and information security, as well as computer science and technology.

This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.

This book introduces readers to a reconfigurable chip architecture for future wireless communication systems, such as 5G and beyond. The proposed architecture perfectly meets the demands for future mobile communication solutions to support different standards, algorithms, and antenna sizes, and to accommodate the evolution of standards and algorithms. It employs massive MIMO detection algorithms, which combine the advantages of low complexity and high parallelism, and can fully meet the requirements for detection accuracy. Further, the architecture is implemented using ASIC, which offers high energy efficiency, high area efficiency and low detection error. After introducing massive MIMO detection algorithms and circuit architectures, the book describes the ASIC implementation for verifying the massive MIMO detection. In turn, it provides detailed information on the proposed reconfigurable architecture: the data path and configuration path for massive MIMO detection algorithms, including the processing unit, interconnections, storage mechanism, configuration information format, and configuration method.